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| IN74HCT157A QUAD 2-INPUT DATA SELECTORS/MULTIPLEXER High-Performance Silicon-Gate CMOS The IN74HCT157A is identical in pinout to the LS/ALS157. This device may be used as a level converter for interfacing TTL or NMOS outputs to High Speed CMOS inputs. This device routes 2 nibbles (A or B) to a single port (Y) as determined by the Select input. The data is presented at the outputs in noninvertered form. A high level on the Output Enable input sets all four Y outputs to a low level. * TTL/NMOS Compatible Input Levels * Outputs Directly Interface to CMOS, NMOS, and TTL * Operating Voltage Range: 4.5 to 5.5 V * Low Input Current: 1.0 A ORDERING INFORMATION IN74HCT157AN Plastic IN74HCT157AD SOIC TA = -55 to 125 C for all packages PIN ASSIGNMENT LOGIC DIAGRAM PIN 16 =VCC PIN 8 = GND FUNCTION TABLE Inputs Outputs Output Select Y0-Y3 Enable H X L L L A0-A3 L H B0-B3 X=don't care A0-A3,B0-B3=the levels of the respective Data-Word Inputs 1 IN74HCT157A MAXIMUM RATINGS* Symbol Parameter Value Unit VCC DC Supply Voltage (Referenced to GND) -0.5 to +7.0 V VIN DC Input Voltage (Referenced to GND) -1.5 to VCC +1.5 V VOUT DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V IIN DC Input Current, per Pin mA 20 IOUT DC Output Current, per Pin mA 25 ICC DC Supply Current, VCC and GND Pins mA 50 PD Power Dissipation in Still Air, Plastic DIP+ 750 mW SOIC Package+ 500 Tstg Storage Temperature -65 to +150 C 260 TL Lead Temperature, 1 mm from Case for 10 C Seconds (Plastic DIP or SOIC Package) * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/C from 65 to 125C SOIC Package: : - 7 mW/C from 65 to 125C RECOMMENDED OPERATING CONDITIONS Symbol Parameter VCC DC Supply Voltage (Referenced to GND) VIN, VOUT DC Input Voltage, Output Voltage (Referenced to GND) TA Operating Temperature, All Package Types t r, tf Input Rise and Fall Time (Figure 1 Min 4.5 0 -55 0 Max 5.5 VCC +125 500 Unit V V C ns This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND(VIN or VOUT)VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. 2 IN74HCT157A DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND) Guaranteed Limit VCC Symbol Parameter Test Conditions V 25 C 85 125 to C C -55C VOUT=0.1 V or VCC-0.1 V 4.5 VIH Minimum High2.0 2.0 2.0 Level Input 5.5 2.0 2.0 2.0 IOUT 20 A Voltage VOUT=0.1 V or VCC-0.1 V 4.5 VIL Maximum Low 0.8 0.8 0.8 Level Input 5.5 0.8 0.8 0.8 IOUT 20 A Voltage VIN=VIH or VIL VOH Minimum High4.5 4.4 4.4 4.4 Level Output 5.5 5.4 5.4 5.4 IOUT 20 A Voltage VIN=VIH or VIL 4.5 3.98 3.84 3.7 IOUT 4.0 mA VIN=VIH or VIL VOL Maximum Low4.5 0.1 0.1 0.1 Level Output 5.5 0.1 0.1 0.1 IOUT 20 A Voltage VIN=VIH or VIL 4.5 0.26 0.33 0.4 IOUT 4.0 mA IIN Maximum Input VIN=VCC or GND 5.5 0.1 1.0 1.0 Leakage Current VIN=VCC or GND ICC Maximum 5.5 4.0 40 160 Quiescent Supply IOUT=0A Current (per Package) VIN=2.4 V, Any One Additional -55C 25C to ICC Quiescent Supply Input 125C VIN=VCC or GND, Other Current Inputs 5.5 2.9 2.4 IOUT=0A Unit V V V V A A mA 3 IN74HCT157A AC ELECTRICAL CHARACTERISTICS(VCC =5.0 V 10%, CL=50pF,Input tr=tf=6.0 ns) Guaranteed Limit Unit Symbol Parameter 25 C 85C 125 to C -55C 27 34 41 ns tPLH, Maximum Propagation Delay, Input A or tPHL B to Output Y (Figures 1and 4) tPLH, Maximum Propagation Delay , Select to 37 46 56 ns tPHL Output Y (Figures 2 and 4) tPLH, Maximum Propagation Delay , Output 30 38 45 ns tPHL Enable to Output Y (Figures 3 and 4) tTLH, tTHL Maximum Output Transition Time, Any 15 19 22 ns Output (Figures 1 and 4) CIN Maximum Input Capacitance 10 10 10 pF Power Dissipation Capacitance (Per Transceiver Channel) Used to determine the no-load dynamic power consumption: PD=CPDVCC2f+ICCVCC Typical @25C,VCC=5.0 V 64 CPD pF Figure 1. Switching Waveforms Figure 2. Switching Waveforms Figure 3. Switching Waveforms Figure 4. Test Circuit 4 IN74HCT157A EXPANDED LOGIC DIAGRAM 5 |
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